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? e94y31-te sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25?) supply voltage v dd ?.5 to +7.0 v input voltage v i ?.5 to v dd +0.5 v output voltage v i ?.5 to v dd +0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd +3.5 to +5.5 (+5.0 typ.) v operating temperature topr ?0 to +75 ? description cxd1803aq/ar is a cd-rom decoder lsi with a built-in adpcm decoder. features compatible with cd-rom, cd-i and cd-rom xa formats real time error correction capable of handling up to quadruple speed playback connectable with standard sram of up to 2m-bit (256k-byte) connectable with standard dram of up to 2m-bit (256k-byte) (2 dram's of 256k 4) all audio output sampling frequencies: 132.3 khz (built-in oversampling filter) de-emphasis digital filter digital attenuator connectable directly with sony's scsi controller cxd1185cq. applications cd-rom drives structure silicon gate cmos ic cd-rom decoder cxd1803aq cxd1803ar 100 pin qfp (plastic) 100 pin lqfp (plastic) cxd1803aq/ar
? cxd1803aq/ar block diagram the pin numbers in the diagram are for the cxd1803aq. priority resolver ma0-16 xme0 xme1 dram xmoe xmwr mdb0-7,p d0-7 xcs xrd xwr xint a0-a4 emp dato lrco wcko bcko mute td0-5 sd0-7 vdd gnd lrck data bclk c2po xtl2 xtl1 cksl rmck clk hclk 84 85 86 87 76 77 80 81 83 82 88 94 93 92 91 95 xrst 21 63 64 26 27 30 | 34 36 23 96 | 100 4, 9 15,21 29,35 40,47 54,60 65,71 79,90 3 28 53 78 1,2,5?,10,11 16 14 13 12 17?0,22 66?0,72?5 57 62 39,41?6,48?2,55,56,58,59,61 address gen dma sequencer cdp i/f galois field syndrome gen ecc corrector c l g o e c n k sub cpu i/f host i/f adpcm decoder digital fileter dac i/f 24 25 37 38 xsrd xswr sdrq xsac dma fifo descrambler sync control 89
? cxd1803aq/ar pin description pin no. symbol i/o description qr 1 99 d0 i/o sub cpu data bus 2 100 d1 i/o sub cpu data bus 31 v dd power supply (+5 v) 4 2 gnd ground 5 3 d2 i/o sub cpu data bus 6 4 d3 i/o sub cpu data bus 7 5 d4 i/o sub cpu data bus 8 6 d5 i/o sub cpu data bus 9 7 gnd ground 10 8 d6 i/o sub cpu data bus 11 9 d7 i/o sub cpu data bus 12 10 xcs i ic select negative logic signal from sub cpu 13 11 xrd i strobe negative logic signal to read this ic internal register from sub cpu 14 12 xwr i strobe negative logic signal to write this ic internal register from sub cpu 15 13 gnd ground 16 14 xint o interrupt request negative logic signal from ic to sub cpu 17 15 a0 i sub cpu address 18 16 a1 i sub cpu address 19 17 a2 i sub cpu address 20 18 a3 i sub cpu address 21 19 dram i memory type selection signal. high: dram, low: sram 22 20 a4 i sub cpu address 23 21 td0 i/o test input/output 24 22 xsrd o strobe negative logic signal to read scsi controller internal register 25 23 xswr o strobe negative logic signal to write scsi controller internal register 26 24 sd0 i/o scsi controller data bus 27 25 sd1 i/o scsi controller data bus 28 26 v dd power supply (+5 v) 29 27 gnd ground 30 28 sd2 i/o scsi controller data bus 31 29 sd3 i/o scsi controller data bus 32 30 sd4 i/o scsi controller data bus 33 31 sd5 i/o scsi controller data bus 34 32 sd6 i/o scsi controller data bus
? cxd1803aq/ar pin no. symbol i/o description qr 35 33 gnd ground 36 34 sd7 i/o scsi controller data bus 37 35 sdrq i scsi data request positive logic signal 38 36 xsac o scsi acknowledge negative logic signal 39 37 ma0 o buffer memory address (lsb) 40 38 gnd ground 41 39 ma1 o buffer memory address 42 40 ma2 o buffer memory address 43 41 ma3 o buffer memory address 44 42 ma4 o buffer memory address 45 43 ma5 o buffer memory address 46 44 ma6 o buffer memory address 47 45 gnd ground 48 46 ma7 o buffer memory address 49 47 ma8 o buffer memory address 50 48 ma9 o buffer memory address 51 49 ma10 o buffer memory address 52 50 ma11 o buffer memory address 53 51 v dd power supply (+5 v) 54 52 gnd ground 55 53 ma12 o buffer memory address 56 54 ma13 o buffer memory address 57 55 xme0 o memory chip enable negative logic signal 58 56 ma14 o buffer memory address 59 57 ma15 o buffer memory address 60 58 gnd ground 61 59 ma16 o buffer memory address xras dram ras signal 62 60 xme1 o memory chip enable negative logic signal 63 61 xmoe o buffer memory output enable negative logic signal xcas dram cas signal 64 62 xmwr o buffer memory write enable negative logic signal 65 63 gnd ground 66 64 mdb0 i/o buffer memory data bus 67 65 mdb1 i/o buffer memory data bus
? cxd1803aq/ar pin no. symbol i/o description qr 68 66 mdb2 i/o buffer memory data bus 69 67 mdb3 i/o buffer memory data bus 70 68 mdb4 i/o buffer memory data bus 71 69 gnd ground 72 70 mdb5 i/o buffer memory data bus 73 71 mdb6 i/o buffer memory data bus 74 72 mdb7 i/o buffer memory data bus 75 73 mdbp i/o buffer memory data bus (for error flag) 76 74 xtl2 o crystal oscillation circuit output 77 75 xtl1 i crystal oscillation circuit input (16.9344 mhz) 78 76 v dd power supply (+5 v) 79 77 gnd ground 80 78 clk o 16.9344 mhz clock output 81 79 hclk o 8.4672 mhz clock output 82 80 cksl i clock select signal for cd-rom decoder 83 81 rmck i clock signal for cd-rom decoder 84 82 lrck i lr clock signal from cd dsp (for discriminating l, r channels ) 85 83 data i data signal from cd dsp 86 84 bclk i data pin strobe clock signal (bit clock) 87 85 c2po i error flag (c2 pointer) positive logic signal from cd dsp 88 86 emp i emphasis on positive logic signal from cd dsp 89 87 xrst i reset negative logic signal 90 88 gnd ground 91 89 dato o data signal to dac (d/a converter) 92 90 lrco o lr clock signal to dac 93 91 wcko o word lock signal to dac 94 92 bcko o bit clock signal to dac 95 93 mute o mute positive logic signal 96 94 td5 i/o test input/output 97 95 td4 i/o test input/output 98 96 td3 i/o test input/output 99 97 td2 i/o test input/output 100 98 td1 i/o test input/output note: the pin numbers in the column "q" are for the cxd1803aq, and those in the column "r" are for the cxd1803ar.
? cxd1803aq/ar electrical characteristics dc characteristics (v dd = 5 v 10%, v ss = 0 v, topr = ?0 - 75?) item symbol conditions min. typ. max. unit ttl input level pin * 1 high level input voltage v ih1 2.2 v ttl input level pin * 1 low level input voltage v il1 0.8 v cmos input level pin * 2 high level input voltage v ih2 0.7v dd v cmos input level pin * 2 low level input voltage v il2 0.3v dd v cmos schmitt input level pin * 3 high level input voltage v ih4 0.8v dd v cmos schmitt input level pin * 3 low level input voltage v il4 0.2v dd v cmos schmitt input level pin * 3 input voltage hysteresis v ih4 to v il4 0.6 v ttl schmitt input level pin * 4 high level input voltage v ih5 2.2v v ttl schmitt input level pin * 4 low level input voltage v il5 0.8v v ttl schmitt input level pin * 4 input voltage hysteresis v ih4 to v il4 0.4 v bidirectional pin with pull-up resistor * 5 input current i il3 v in =0v ?0 ?00 ?40 ? pin with pull-up resistor * 6 input current i il4 v in =0v ?0 ?00 ?40 ? high level output voltage * 7 v oh1 i oh =?ma v dd -0.8 v low level output voltage * 7 v ol1 i ol =?ma 0.4 v input leakage current * 8i i1 v in =v ss ?0 10 ? or v dd output leakage current * 9i oz high-impedance ?0 40 ? state oscillation cell * 10 high level input voltage v ih4 0.7v dd v oscillation cell low level input voltage v il4 0.3v dd v oscillation cell logic threshold value lv th 0.5v dd v oscillation cell feedback resistance value r fb v in =v ss 250k 1m 2.5m or v dd oscillation cell high level output voltage v oh2 i oh =?ma 0.5v dd v oscillation cell low level output voltage v ol2 i ol =3ma 0.5v dd v
? cxd1803aq/ar dc characteristics (v dd = 3.5 v, v ss = 0 v, topr = ?0 - 75?) item symbol conditions min. typ. max. unit ttl input level pin * 1 high level input voltage v ih1 2.2 v ttl input level pin * 1 low level input voltage v il1 0.6 v cmos input level pin * 2 high level input voltage v ih2 0.7v dd v cmos input level pin * 2 low level input voltage v il2 0.3v dd v cmos schmitt input level pin * 3 high level input voltage v ih4 0.8v dd v cmos schmitt input level pin * 3 low level input voltage v il4 0.2v dd v cmos schmitt input level pin * 3 input voltage hysteresis v ih4 to v il4 0.5 v ttl schmitt input level pin * 4 high level input voltage v ih5 2.2v v ttl schmitt input level pin * 4 low level input voltage v il5 0.6v v ttl schmitt input level pin * 4 input voltage hysteresis v ih5 to v il4 0.3 v bidirectional pin with pull-up resistor * 5 input current i il3 v in =0v ?0 ?0 ?10 ? pin with pull-up resistor * 6 input current i il4 v in =0v ?0 ?5 ?0 ? high level output voltage * 7v oh1 i oh =?.6ma v dd -0.8 v low level output voltage * 7v ol1 i ol =3.2ma 0.4 v input leakage current * 8 i i1 v in =v ss ?0 10 ? or v dd output leakage current * 9i oz high-impedance ?0 40 ? state oscillation cell * 10 high level input voltage v ih4 0.7v dd v oscillation cell low level input voltage v il4 0.3v dd v oscillation cell logic threshold value lv th 0.5v dd v oscillation cell feedback resistance value r fb v in =v ss 1.2m 2.5m 5m or v dd oscillation cell high level output voltage v oh2 i oh =?.3ma 0.5v dd v oscillation cell low level output voltage v ol2 i ol =1.3ma 0.5v dd v
? cxd1803aq/ar * 1. d7 to 0, a4 to 0, xwr, xrd, xcs, mdb7 to 0, mdbp, sd7 to 0, td7 to 0 * 2. data, lrck, c2po, emp, cksl, rmck * 3. bclk, xrst * 4. a4 to 0, xwr, xrd, xcs, sdrq * 5. d7 to 0, mdb7 to 0, mdbp, sd7 to 0, td7 to 0 * 6. cksl * 7. all output pins except xtl2 * 8. all input pins except * 5, * 6, and xtl1 * 9. hint * 10. input: xtl1, output: xtl2 i/o capacitance (v dd = v i = 0 v, f = 1 mhz) item symbol min. typ. max. unit input pin c in 9pf output pin c out 11 pf i/o pin c out 11 pf
? cxd1803aq/ar ac characteristics (v dd = 5 v?0%, v ss = 0 v, topr = ?0 to 75?, output load = 50 pf) the values in parentheses on the tables for v dd = 3.5 v, v ss = 0 v, topr = ?0 to 75?, output load = 50 pf. those without parentheses for v dd = 5 v?0% and 3.5 v. 1. sub cpu interface (1) read note) "&" indicates "and". (2) write a0 xrd d7-0 xcs tsar tdrd tfrd trrl thar item symbol min. typ. max. unit address setup time (for xcs & xrd ) tsar 30 (70) ns address hold time (for xcs & xrd - ) thar 20 (50) ns data delay time (for xcs & xrd ) tdrd 60 (100) ns data float time (for xcs & xrd - ) tfrd 0 15 (25) ns low level xrd pulse width trrl 100 (150) ns a0 xwr d7-0 xcs tsaw tsdw thdw twwl thaw item symbol min. typ. max. unit address setup time (for xcs & xwr ) tsaw 30 (70) ns address hold time (for xcs & xwr - ) thaw 20 (50) ns data setup time (for xcs & xwr ) tsdw 40 (70) ns data hold time (for xcs & xwr - ) thdw 10 (30) ns low level xwr pulse width twwl 50 (80) ns
?0 cxd1803aq/ar 2. cd dsp interface bclk lrck c2po data thb2 tsb2 tbck tsb1 thb1 tbck bclk lrck c2po data thb2 tsb2 tbck tsb1 thb1 tbck bckred='h' bckred='l' item symbol min. typ. max. unit bclk frequency fbck 11.3 mhz bclk pulse width tbck 88 ns data setup time (for bclk) tsb1 20 ns data hold time (for bclk) thb1 20 ns lrck, c2po setup time (for bclk) tsb2 20 ns lrck, c2po hold time (for bclk) thb2 20 ns
?1 cxd1803aq/ar 3. dram interface (1) read (2) write xras ma9-0 xmwr xcas tcdd tras trcd tcas trc tasr 'h' trah tasc tcah trdd tcdh row column mdb7-0, p xras ma9-0 xmwr xcas tds tras trcd tcas trc tasr trah tasc tcah tdh row column mdb7-0, p twcs twch
?2 cxd1803aq/ar item symbol min. typ. max. unit random read/write cycle time trc 4tw ns ras pulse width tras 2tw ns ras cas delay time trcd tw ns cas pulse width tcas tw ns row address setup time tasr 10 ns row address hold time trah 20 ns column address setup time tasc 0 ns column address hold time tcah 20 ns delay time from ras trdd 2tw-20 ns delay time from cas tcdd tw-20 ns hold time from cas tcdh 0 ns write command setup time twcs 10 ns write command hold time twcs 20 ns data output setup time tds tw ns data output hold time tds tw ns
?3 cxd1803aq/ar 4. sram interface (1) read xmwr='h' (2) write xmoe='h' item symbol min. typ. max. unit address setup time (for xmoe ) tsao tw-30 ns address hold time (for xmoe - ) thoa tw-10 ns data setup time (for xmoe - ) tsdo 50 (100) ns data hold time (for xmoe - ) thod 10 (20) ns low level xmoe pulse width trrl 2tw ns ma16-0 mdb7-0,p xmoe taso trrl tsdo thod thoa ma16-0 mdb7-0,p xmwr tsaw twwl tdwd tfwd thwa item symbol min. typ. max. unit address setup time (for xmwr ) tsaw tw-30 ns address hold time (for xmwr - ) thwa tw-10 ns data delay time (for xmwr ) tdwd 10 ns data float time (for xmwr - ) tfwd 10 ns low level xmmr pulse width twwl 2tw ns
?4 cxd1803aq/ar 5. scsi controller interface (1) read item symbol min. typ. max. unit xsac fall time (for sdrq - ) tdda 5 tw ns xsrd delay time (for xsac ) tdaw 0 ns xsac delay time (for xsrd - ) tdar tw ns data setup time (for xsrd ) tsdr 20 (60) ns data hold time (for xsrd - ) thdr 10 (30) ns low level xsrd pulse width trrl t 1 ns sdrq setup time (for xsac - ) tsdq 15 (30) ns xsac fall time (for xsac - ) tsac tw ns sdrq xsrd xsac tdda twwl tdaw tdar tasc tsdq trrl tsdr thdr sd7 to 0
?5 cxd1803aq/ar item symbol min. typ. max. unit xsac fall time (for sdrq - ) tdda 5 tw ns xswr delay time (for xsac ) tdaw tw ns xsac delay time (for xswr - ) tdwa tw ns data setup time (for xswr - ) tsdr 2 tw-30 ns data hold time (for xswr - ) thdr tw-10 ns low level xswr pulse width twwl t2 ns sdrq setup time (for xsac - ) tsdq 15 (30) ns xsac fall time (for xsac - ) tsac tw ns (2) write sdrq xswr xsac tdda twwl tdaw tdwa tsac tsdq tsdr thdr sd7 to 0 here: 2 tw: 3cyclemode t 1 =3 tw: 4cyclemode 4 tw: 5cyclemode tw: 3cyclemode t 2 =2 tw: 4cyclemode 3 tw: 5cyclemode tw is the cd-rom decoder clock cycle. y t y t
?6 cxd1803aq/ar 6. dac interface bcko wcko dato tbco thbo tsbo lrco tbco tsbo thbo item symbol min. typ. max. unit bcko frequency fbco 8.4672 mhz bcko pulse width tbco 50 ns dato, wco1, wco2, lrco setup time (for bcko - ) tsbo 30 ns dato, wco1, wco2, lrco hold time (for bcko - ) thbo 30 ns
?7 cxd1803aq/ar 7. xtl1 and xtl2 pins (1) for self-excited oscillation (2) when a pulse is input to xtl1 pin note: synchronize the xtl1 clock signal with that of the cd dsp. (use the clock signal from the same oscillator.) 8. rmck pin note: the maximum rmck frequency is 35.0 mhz, when v dd = 5 v ?%, playback at quadruple normal speed can be accommodated when a clock signal with a frequency double 16.9344 mhz or more is input to rmck. item symbol min. typ. max. unit oscillation frequency fmax 16.9344 mhz vihx vdd/2 vihx * 0.9 tw twhx vilx * 2 tr twlx tf vilx item symbol min. typ. max. unit high level pulse width twhx 20 ns low level pulse width twlx 20 ns pulse cycle tw 59 ns input high level vihx v dd -1.0 ns input low level vilx 0.8 ns rise time tr 15 ns fall time tf 15 ns item symbol min. typ. max. unit frequency frmck 33.3 (23.4) mhz
?8 cxd1803aq/ar description of functions 1. pin description the pin description by function is given below. 1.1.cd player interface (5 pins) this enables direct connection with the digital signal processor lsi for sony's cd players. digital signal processor lsi for cd applications are hereafter called "cd dsp". see 2-1-1 for the data formats. (1) data (data: input) serial data stream from cd dsp. (2) bclk (bit clock: input) bit clock signal; data signal strobe. (3) lrck (lr clock: input) lr clock signal; indicates left and right channels of data signals. (4) c2po (c2 pointer: input) c2 pointer signal; indicates that an error is contained in data input. (5) emp (emphasis: input) emphasis positive logic signal; indicates that emphasis has been applied to data from cd dsp. 1.2.buffer memory interface (30 pins) this is connected with a 32k-byte (256k-bit) or 128k-byte (1m-bit) standard sram; also connected with 256k-byte standard dram (two drams of 128k-byte). (1) xmwr (buffer memory write: output) data write strobe negative logic output signal to buffer memory. (2) xmoe/xcas (buffer memory output enable/column address strobe: output) when connected to sram, data read strobe negative logic output signal to buffer memory. when connected to dram, xcas (column address strobe negative logic) signal. (3) ma0 to 15 (buffer memory address: output) address signals to buffer memory. when connected to dram, ma0 to 8 are valid. (4) ma16/xras (buffer memory address/row address strobe: output) when connected to sram, address signal to buffer memory. xras (row address strobe negative logic) signal when connected to dram. (5) xme0, 1 (buffer memory chip enable: output) when connected to a chip sram, chip enable negative logic signal to buffer memory. not used when connected to dram. (6) mdb0 to 7, p (buffer memory data bus: bus) data bus signals to buffer memory; pulled up by standard 25k resistor; mdbp pin is left open when connected to an 8-bit/word sram. (7) dram (buffer memory dram: input) high is input when dram is connected as buffer memory. low is input when sram is connected as buffer memory.
?9 cxd1803aq/ar 1.3.sub cpu interface (17 pins) (1) xwr (sub cpu write: input) strobe negative logic input signal for writing ic internal register. (2) xrd (sub cpu read: input) strobe negative logic input signal for reading ic internal register status. (3) d0 to 7 (sub cpu data bus: input/output) 8-bit data bus. (4) a0 to 4 (sub cpu address: input) address signal for selecting ic internal register from sub cpu. (5) xint (sub cpu interrupt: output) interrupt request negative logic signal to sub cpu. (6) xcs (chip select: input) ic select negative logic signal from sub cpu. 1.4.scsi controller interface (13pins) (1) sdrq (scsi data request: input) dma data request positive logic signal from scsi controller ic. (2) xsac (scsi dma acknowledge: output) dma acknowledge negative logic signal to scsi controller ic. (3) xswr (scsi write: negative logic output) data write strobe output to scsi controller ic. (4) xsrd (scsi read: negative logic output) data read strobe output to scsi controller ic. (5) sd0 to 7 (scsi controller bus: input/output) scsi controller data bus signal. 1.5.dac interface (4 pins) the output format to dac is shown in fig. 1-1. (1) bcko (bit clock output: output) bit clock output signal to d/a converter. (2) wcko (word clock output: output) word clock output signal to d/a converter. (3) lrco (lr clock output: output) lr clock output signal to d/a converter. (4) dato (data output: output) data output signal to d/a converter.
?0 cxd1803aq/ar bcko dato wcko lrco 123 45 67 8 9 10 11 12 13 14 15 16 12 34 56789 10 11 12 13 14 15 16 16 123 4 17 msb l ch lsb 32 msb r ch 49 64 fig. 1-1 output format to d/a converter
?1 cxd1803aq/ar 1.6.others (16 pins) (1) mute (mute: output) outputs high when da data (dato) is muted. (2) xrst (reset: input) chip reset negative logic input signal. (3) xtl1 (crystal 1: input) (4) xtl2 (crystal 2: output) a 16.9344 mhz crystal oscillator is connected between xtl1 and xtl2. (the capacitor value depends on the crystal oscillator.) alternatively, a 16.9344 mhz clock signal is input to the xtl1 pin. (5) clk (cock: output) outputs a 16.9344 mhz clock signal. the output can be fixed low when this signal is not used. (6) hclk (half clock: output) outputs an 8.4672 mhz clock. the output can be fixed low when this signal is not used. (7) cksl (clock select: input) high or open: the ic is operated by the xtl1 clock. low: the audio block (adpcm decoder and digital filter) is operated by the xtl1 clock, and the cd-rom decoder block is operated by the rmck clock. this pin is pulled up by a standard 50k resistor in the ic . (8) rmck (rom clock: input) when the cksl pin is set low, the clock of the cd-rom decoder block is input. when it is high or left open, fix the rmck pin high or low. (9) td0 to 5 (test data 0 to 5: input/output) data pins for testing the ic . they are pulled up by a 25k standard resistor and are normally left open.
?2 cxd1803aq/ar 2. sub cpu registers 2.1.write registers 2.1.1. drvif (drive interface) register this register controls the connection mode with the cd dsp. after the ic is reset, the sub cpu sets this register according to the cd dsp to be connected. bit 7: c2pl1st (c2po lower byte first) high: when two bytes of data are input, c2po inputs the lower byte first followed by the upper byte. low: when two bytes of data are input, c2po inputs the upper byte first followed by the lower byte. here, "upper byte" means the upper 8 bits including msb from the cd dsp and "lower byte" means the lower 8 bits including lsb from the cd dsp. for example, the header minute byte is the lower byte and the second byte, the upper byte. bit 6: lchlow (lch low) high: when lrck is low, determined to be the left channel data. low: when lrck is high, determined to be the left channel data. bit 5: bckred (bclk rising edge) high: data is strobed at the rising edge of bclk. low: data is strobed at the falling edge of bclk. bits 4,3: bckmd1, 0 (bclk mode1, 0) these bits are set according to the number of clocks output for bclk during one wclk cycle by the cd digital signal processing lsi (cd dsp). bit 2: lsb1st (lsb first) high: connected with the cd dsp which outputs data with lsb first. low: connected with the cd dsp which outputs data with msb first. bits 1,0: reserved normally set low. any change of each bit in this register must be made in the decoder disable status. table 2-1-1 indicates the setting values for bits 7 to 2 when this ic is connected to sony's cd dsp. figs. 2-1-1(1) to (3) are input timing charts. bckmd1 bckmd0 'l' 'l' 16bclks/wclk 'l' 'h' 24bclks/wclk 'h' 'x' 32bclks/wclk
?3 cxd1803aq/ar bclk data c2po lrck l15 l0 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 l14 r0 24123456789101112131415161718192021222324123 rch lsb lch msb for lower byte for upper byte lch lsb bclk data c2po lrck l15 l0 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 l14 r0 rch lsb lch msb for lower byte for upper byte lch lsb 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 123 24 bclk data c2po lrck r0 r15 r14 r13 r12 r11 r10 r9 r8 r6 r5 r3 r2 r1 l15 1 2 3 4 5 6 7 8 9 1011 121314 1516171819 20 21222324 1 2 3 lch msb rch lsb for lower byte for upper byte rch msb r7 l14 25 26 27 28 29 30 31 32 4 31 32 r4 fig. 2-1-1 (1) cdl30 and 35 series timing chart fig. 2-1-1 (2) cdl40 series timing chart (48-bit slot mode) fig. 2-1-1 (3) cdl40 series timing chart (64-bit slot mode)
?4 cxd1803aq/ar dr vif register sony cd dsp bit7 bit6 bit5 bit4 bit3 bit2 timing chart c2po lrck bedg bck1 bck0 lsb cdl30 series l l l l h l fig. 2-1-1(1) cdl35 series cdl40 series l l h l h l fig. 2-1-1 (2) (48-bit slot mode) cdl40 series l h l h x h fig. 2-1-1(3) (64-bit slot mode) table 2-1-1 drvif register settings cxd1125q/qz, cxd1130q/qz, cxd1135q/qz cdl30 series cxd1241q/qz, cxd1245q, cxd1246q/qz cxd1247q/qz/r, etc. cdl35 series cxd1165q, cxd1167q/qz/r, etc. cdl40 series cxd2500q/qz, etc. note 1) 2.1.2. config1 (configuration 1) register this register is set depending on the ic peripheral hardware. the sub cpu sets this register after the ic is reset. bit 7: reserved normally set low. bit 6: xslow the number of clock signals per dma1 cycle is determined by this bit. high: 4 clock signals low: 12 clock signals set low when a low-speed sram is connected for v dd = 3.5 v. when xslow is low, erasure correction and double speed playback are prohibited. bit 5: reserved normally set low. bits 4,3: ramsz1, 0 (ram size 1, 0) bit 2: 9bitram these bits are set depending on the size of the buffer memory connected to the ic. refer to chapter 3 for information on buffer memory connection. ramsz1 ramsz0 9bitram memory size 'l' 'l' 'l' 32k w 8 b 'l' 'l' 'h' 32k w 9 b 'l' 'h' 'l' 64k w 8 b 'l' 'h' 'h' 64k w 9 b 'h' 'l' 'l' 128k w 8 b 'h' 'l' 'h' 128k w 9 b 'h' 'h' 'l' 256k w 8 b 'h' 'h' 'h' 256k w 9 b
?5 cxd1803aq/ar bit 1: clkdis (clk disable) high: the clk pin is fixed low. low: a 16.9344 mhz clock signal is output from the clk pin. bit 0: hclkdis (half clk disable) high: the hclk pin is fixed low. low: an 8.4672 mhz clock signal is output from the hclk pin. 2.1.3. config2 (configuration 2) register this register is set depending on the ic peripheral hardware. the sub cpu sets this register after the ic has been reset. bits 7, 6: scyc1, 0 (scsi dma cycle 1, 0) data transfer between the ic and the scsi control ic is executed by the following number of clock signals. bit 5: spectl (sound parameter error control) bit 4: spmctl (sound parameter majority control) these two bits control the processing of the sound parameters for adpcm playback. bit 3: smbf2 (sound map buffer 2) indicates the number of buffer surfaces for the sound map adpcm. high: 2 buffer surfaces for the sound map low: 3 buffer surfaces for the sound map bit 2: damixdis (digital audio mixer disable) high: attenuator and mixer are not activated for cd-da. low: attenuator and mixer are activated for cd-da. bit 1: dacouten (dac out enable) high: clock signals are output from the wcko, lrco and bcko pins even for muting. low: the wcko, lrco and bcko pins are set low for muting. bit 0: prtyctl (priority control) when double speed playback with erasure correction is carried out with the cd-rom decoder clock frequency at 18 mhz or less, this bit goes high. in this case, priority is given to buffer access for ecc, and the data transfer rate to the scsi controller drops. scyc1 scyc0 'l' 'l' 3 clock signals 'l' 'h' 4 clock signals 'h' 'x' 5 clock signals
?6 cxd1803aq/ar 2.1.4. decctl (decoder control) register bit 7: endladr (enable drive last address) high: dladr (drive last address) is enabled when this is set high. when dadrc and dladr become equal while the decoder is in the write-only, real-time correction or cd-da mode, the data writing from the drive into the buffer is stopped. low: dladr (drive last address) is disabled when this is set low. even when dadrc and dladr become equal while the decoder is in the write-only, real-time correction or cd-da mode, the data writing from the drive into the buffer is not stopped. bit 6: eccstr (ecc strategy) high: errors are corrected with consideration given to the error flags of the data. low: errors are corrected with no consideration given to the error flags of the data. in this case, there is no erasure correction. set this bit low when the ic is connected to an 8-bit/word sram. bit 5: modesel (mode select) bit 4: formsel (form select) when autodist is low, the sector is corrected in the mode or form indicated below. bit 3: autodist (auto distinction) high: errors are corrected according to the mode byte and form bit read from the drive. low: errors are corrected according to the modesel and formsel bits (bits 5 and 4). bits 2 to 0:decmd2 to 0 (decoder mode 2 to 0) when the cd-da bit (bit 4) in the chpctl register is to be set high, set the decoder to the disable or cd-da mode. modesel formsel 'l' 'l' mode1 'h' 'l' mode2, from1 'h' 'h' mode2, from2 decmd2 decmd1 decmd0 'l' 'l' 'x' decoder disable 'l' 'h' 'x' monitor-only mode 'h' 'l' 'l' write-only mode 'h' 'l' 'h' real-time correction mode 'h' 'h' 'l' repeat correction mode 'h' 'h' 'h' cd-da mode
?7 cxd1803aq/ar 2.1.5. dladr-l 2.1.6. dladr-m 2.1.7. dladr-h while the decoder is in the write-only, real-time correction or cd-da mode, the last address is set for the buffer write data from the drive. when the endladr bit (bit 7) of the decctl register is high and the data from the drive is written into the address assigned by dladr while the decoder is in any of the above modes, all subsequent writing in the buffer is prohibited. 2.1.8. chpctl (chip control) register bit 7: sm mute (sound map mute) when this is set high, the audio output is muted for sound map adpcm playback. bit 6: rt mute (real time mute) when this is set high, the audio output is muted for real-time adpcm playback. bit 5: cd-da mute when bit 4 is high and this bit is also set high for a cd-da (digital audio) disc playback, the audio output is muted. when bit 4 is low, this bit has no effect on the audio output. bit 4: cd-da high: set high for playing back the audio signals of a cd-da disc. setting this bit high is prohibited for adpcm decode playback. low: set low for not playing back the audio signals of a cd-da disc. bit 3: swopen (sync window open) high: a window for sync mark detection is opened. in this case, the sync protection circuit in the ic is disabled. low: the window for sync mark detection is controlled by the sync protection circuit in the ic. bit 2: rpstart (repeat correction start) sector error correction starts when the decoder is set to the repeat correction mode, making this bit high. this bit is automatically set low when correction starts. therefore, there is no need for the sub cpu to reset low. bit 1: dblspd (double speed) set high for double speed playback. before changing the bit value, switch the cd dsp mode (normal speed playback or double speed playback). bit 0: reserved normally set low.
?8 cxd1803aq/ar 2.1.9. wrdata (cpu buffer write data) the data written in this register is written in the buffer. 2.1.10. intmsk (interrupt mask) register by setting each bit of this register high, the interrupt request from the ic to the sub cpu is enabled depending on the corresponding interrupt status. (in other words, the int pin is made active when its interrupt status is established.) the value of each bit in this register does not affect the corresponding interrupt status. bit 7: drvovrn (drive overrun) the drvovrn status is established when the endladr bit (bit 7) of the decctl register is set high, and dadrc and dladr become equal while the decoder is in the write-only or real-time correction mode. it is also established when they become equal while the decoder is in the cd-da mode regardless of the endladr bit value. bit 6: dectout (decoder time out) the dectout status is established when the sync mark is not detected even after the time it takes to search 3 sectors (40.6 ms at normal speed playback) has elapsed after the decoder has been set to the monitor-only, write-only or real-time correction mode. bit 5: reserved normally set low. bit 4: rtadpend (real time adpcm end) the rtadpend status is established when real-time adpcm decoding is completed for one sector. bit 3: hdmacmp (host dma complete) the hdmacmp status is established when dma is completed by hxfrc. bit 2: decint (decoder interrupt) the decint status is established when the sync mark is detected or inserted while the decoder is in the write-only, monitor-only or real-time correction mode. however, it is not established if the sync mark interval is less than 2352 bytes while the window for its detection is open. the status is established each time one correction is completed when the decoder is in the repeat correction mode. bit 1: bfwrdy (buffer write ready) the bfwrdy status is established when there is more than one sector available for buffer write when the decoder is in the sound map playback mode. the status is also established for any of the following. (1) the sub cpu makes the dmactl register smen bit high. (2) when there is more than one sector of sound map data area after one sector of sound map data is written into buffer memory from the scsi controller (not buffable). (3) when there is an area for sound map data writing on the buffer memory because one sector of sound map adpcm decoding has been completed. bit 0: bfempt (buffer empty) the bfempt status is established when there is no subsequent sector data on the buffer memory after one sector of adpcm decoding is completed during sound map playback.
?9 cxd1803aq/ar 2.1.11. clrctl (clear control) register when each bit of the register is set high, the corresponding chip, status, register, interrupt status and adpcm playback are cleared. after clearing, the bit concerned is automatically set low. therefore, there is no need for the sub cpu to reset low. bit 7: chprst (chip reset) the inside of the ic is initialized when this bit is set high. this bit is automatically set low upon completion of the initialization. bits 6, 5: reserved normally set low. bit 4: rtadpclr (real time adpcm clear) (1) when this is set high for real-time adpcm playback (when the rtadpbsy bit of the decsts register is high): adpcm decoding for playback is suspended. (noise may be generated.) the rtadpend interrupt status is established. (note) the adpen bit (bit 7 of the adpmnt register) must be set low before this bit is set high. (2) setting this bit high when real-time adpcm playback is not being performed has no effect whatsoever. bit 3: smadpclr (sound map adpcm clear) (1) when this is set high for sound map adpcm playback (when the smadpbsy bit of the decsts register is high): adpcm decoding for playback is suspended. (noise may be generated.) the rtadpend interrupt status is established. (2) setting this bit high when sound map adpcm playback is not being performed has no effect whatsoever. bit 2: reserved normally set low. bit 1: pdata (pointer data) the data written to this bit is written in the buffer pointer bit along with the wrdata register value. bit 0: resync the cd dsp and this ic are re-synchronized when this bit is set high. set the bit high by the sub cpu in the following cases: (1) after the drvif register has been set (2) after the dblspd bit (bit 1 of the chpctl register) has been set low. this bit is automatically set low when the cd dsp and this ic are re-synchronized.
?0 cxd1803aq/ar 2.1.12. clrint (clear interrupt status) register when each bit of this register is set high, the corresponding interrupt status is cleared. the bit concerned is automatically set low after its interrupt status has been cleared. therefore, there is no need for the sub cpu to reset low. bit 7: drvovrn (drive overrun) bit 6: dectout (decoder time out) bit 5: reserved normally set low. bit 4: rtadpend (real time adpcm end) bit 3: hdmacmp (host dma complete) bit 2: decint (decoder interrupt) bit 1: bfwrdy (buffer write ready interrupt) bit 0: bfempt (buffer write empty interrupt) 2.1.13. hxfr-l (host transfer-low) 2.1.14. hxfr-h (host transfer-high) bit 7: dishxfrc (disable host transfer counter) high: the completion of the data transfer by hxfrc is disabled for data transfer between the scsi controller and buffer memory. low: the completion of the data transfer by hxfrc is enabled for data transfer between the scsi controller and buffer memory. bit 6: reserved bit 5: hadr17 hadr bit 17 (msb) bit 4: hadr16 hadr bit 16 bit 3: hxfr11 hxfr (host transfer counter) bit 11 (msb) bit 2: hxfr10 hxfr bit 10 bit 1: hxfr9 hxfr bit 9 bit 0: hxfr8 hxfr bit 8 the hxfr (host transfer) register sets the number of data transferred between the scsi controller and buffer memory. the sub cpu sets this number when data is transferred between the scsi controller and buffer memory by setting the dishxfrc bit low. 2.1.15. hadr-l (host address-low) 2.1.16. hadr-m (host address-middle) the hadr (host address) register is for the head addresses of data transfer between the scsi controller and buffer memory. the upper two hadr bits are in hxfr-h.
?1 cxd1803aq/ar 2.1.17. dadrc-l this counter keeps the address for writing the data from the drive into the buffer. when drive data is written into the buffer, the dadrc value is output from ma0 to 17 (when sram is connected). dadrc is incremented each time 1 byte of data is written from the drive into the buffer. the sub cpu sets the head address for buffer writing into dadrc before the decoder operates in the write-only, real-time correction or cd-da mode. the sub cpu can set dadrc at any time. the contents of dadrc should not be changed while the decoder is operating in any of the above modes. 2.1.18. dadrc-m 2.1.19. dadrc-h 2.1.20. cadrc-l this counter keeps the address for writing/reading the data from the sub cpu into the buffer. when drive data is written into the buffer, the dadrc value is output from ma0 to 17 (when sram is connected). dadrc is incremented each time 1 byte of data is written from the drive into the buffer. the sub cpu can set cadrc at any time. 2.1.21. cadrc-m 2.1.22. cadrc-h bit 7: reserved bit 6: cpu src (sub cpu source) this bit is set high when the sub cpu writes data into the buffer. it is set low when the sub cpu reads data from the buffer. bit 5: cdmaen (sub cpu dma enable) this bit is set high when the sub cpu reads or writes data in the buffer memory. bits 4 to 2:reserved bit 1: cadrc bit 17 (msb) bit 0: cadrc bit 16 2.1.23. dmactl (dma control) bit 7: bfrd (buffer read) transfer of (drive) data from the buffer memory to the scsi controller begins when this bit is set high. the bit is automatically set low after transfer is completed. bit 6: bfwr (buffer write) transfer of data from the scsi controller to buffer memory begins when this bit is set high. the bit is automatically set low after transfer is completed. bit 5: smen (sound map enable) set high when sound map adpcm playback is performed. bits 4 to 0:reserved the sub cpu must set these bits low.
?2 cxd1803aq/ar 2.1.24. smci writes the coding information bytes when sound map adpcm playback is performed. bit 6: emphasis set high when an adpcm sector where emphasis has been applied is played back. bit 4: bitlngth (bit length) indicates the bit length of the coding information for adpcm playback. high: 8 bits low: 4 bits bit 2: fs (sampling frequency) indicates adpcm playback sampling frequency. high: 18.9 khz low: 37.8 khz bit 0: s/m (stereo/monaural) indicates the coding information stereo or monaural for adpcm playback. high: stereo low: monaural bits 7, 5, 3, 1: reserved normally set low. 2.1.25. adpmnt bit 7: rtadpen (real-time adpcm enable) the sub cpu sets this high to perform real-time adpcm playback. bits 6 to 0:the upper 7 bits (bits 16 to 10) of the sector head address are written into these bits to perform real-time adpcm playback. adpmnt bit 17 is in rtci register bit 1. any of the following values can be written into this register: 00, 0c, 18, 24, 30, 3c, 54hex (when connected to 32k-byte buffer memory). 2.1.26. rtci writes the coding information bytes when real-time adpcm playback is performed. bit 6: emphasis set high when an adpcm sector where emphasis has been applied is played back. bit 4: bitlngth (bit length) indicates the bit length of the coding information for adpcm playback. high: 8 bits low: 4 bits bit 2: fs (sampling frequency) indicates sampling frequency of adpcm playback. high: 18.9 khz low: 37.8 khz bit 1: adpmnt17 adpmnt bit 17 (msb) bit 0: s/m (stereo/monaural) indicates the coding information stereo or monaural for adpcm playback. high: stereo low: monaural bits 7, 5, 3: reserved normally set low.
?3 cxd1803aq/ar 2.1.27. atv (attenuation value) register 0 2.1.28. atv (attenuation value) register 1 2.1.29. atv (attenuation value) register 2 2.1.30. atv (attenuation value) register 3 the attenuation values are set in these registers. setting 81 hex or higher in these registers is prohibited. when bits 7 to 0 of these registers are "b7" to "b0", the attenuation (db) is as follows: attenuation = 201og (b7 2 0 +b6 2 -1 +b5 2 -2 +b4 2 -3 +b3 2 -4 +b2 2 -5 +b1 2 -6 +b0 2 7 the relationship expressed in the above formula and atv register settings are given in the following table. df atv0 atv2 atv3 atv1 l r adpcm decoder + +
?4 cxd1803aq/ar setting attenuation setting attenuation setting attenuation 80 0.00 55 3.56 2a 9.68 7f 0.07 54 3.66 29 9.89 7e 0.14 53 3.76 28 10.10 7d 0.21 52 3.87 27 10.32 7c 0.28 51 3.97 26 10.55 7b 0.35 50 4.08 25 10.78 7a 0.42 4f 4.19 24 11.02 79 0.49 4e 4.30 23 11.26 78 0.56 4d 4.41 22 11.51 77 0.63 4c 4.53 21 11.77 76 0.71 4b 4.64 20 12.04 75 0.78 4a 4.76 1f 12.32 74 0.86 49 4.88 1e 12.60 73 0.93 48 5.00 1d 12.90 72 1.01 47 5.12 1c 13.20 71 1.08 46 5.24 1b 13.52 70 1.16 45 5.37 1a 13.84 6f 1.24 44 5.49 19 14.19 6e 1.32 43 5.62 18 14.54 6d 1.40 42 5.75 17 14.91 6c 1.48 41 5.89 16 15.30 6b 1.56 40 6.02 15 15.70 6a 1.64 3f 6.16 14 16.12 69 1.72 3e 6.30 13 16.57 68 1.80 3d 6.44 12 17.04 67 1.89 3c 6.58 11 17.54 66 1.97 3b 6.73 10 18.06 65 2.06 3a 6.88 0f 18.62 64 2.14 39 7.03 0e 19.22 63 2.23 38 7.18 0d 19.87 62 2.32 37 7.34 0c 20.56 61 2.41 36 7.50 0b 21.32 60 2.50 35 7.66 0a 22.14 5f 2.59 34 7.82 09 23.06 5e 2.68 33 7.99 08 24.08 5d 2.77 32 8.16 07 25.24 5c 2.87 31 8.34 06 26.58 5b 2.96 30 8.52 05 28.16 5a 3.06 2f 8.70 04 30.10 59 3.16 2e 8.89 03 32.60 58 3.25 2d 9.08 02 36.12 57 3.35 2c 9.28 01 42.14 56 3.45 2b 9.47 00 relationship between atv register settings and attenuation amounts all written registers, except the atv0 and atv2 registers, are 00 hex when the ic is reset (both hard and soft reset). the atv0 and atv2 registers are 80 hex when the ic is reset. "hard reset" means that the xrst pin is set low. "soft reset" means that the sub cpu resets the ic.
?5 cxd1803aq/ar 2.2. read registers in the descriptions of the eccsts, decsts, hdrflg, hcr, shdr and cmadr-h registers, the current sector denotes the sector for which these registers are valid for the decoder interrupt (decint). in the monitor-only or write-only mode, the sector sent from the cd dsp immediately before the decoder interrupt is called the current sector. in the real-time correction mode and repeat correction mode, the current sector is that in which error detection correction has been completed. 2.2.1. eccsts (ecc status) bit 7: edcall0 (edc all 0) this is high when there are no error flags in all the 4 edc parity bytes of the current sector and their values are all 00h. bit 6: erinblk (erasure in block) (1) when the decoder is operating in the monitor-only, write-only or real-time mode which prohibits erasure correction, this indicates that at least a 1-byte error flag (c2po) has been raised in the data excluding the sync mark from the current sector cd dsp. (2) when the decoder is operating in the real-time correction mode which performs erasure correction, this indicates that at least a 1-byte error flat (mdbp) has been raised in the data excluding the sync mark from the current sector cd dsp. bit 5: corinh (correction inhibit) this is high if the current sector mode and form could not be determined when the autodist bit of the decctl register is set high. ecc or edc is not executed in this sector. the corinh bit is invalid when autodist is set low. it is high in any of the conditions below when the autodist bit is set high. (1) when the c2 pointer of the mode byte is high (2) when the mode byte is a value other than 01 hex or 02 hex . (3) when the mode byte is 02 hex and the c2 pointer is high in the submode byte bit 4: cordone (correction done) indicates that there is an error corrected byte in the current sector. bit 3: edcok indicates that an edc check has found no errors in the current sector. bit 2: eccok indicates that there are no more errors from the header byte to p parity byte in the current sector. (bit 2 = don't care in the mode2, form2 sectors.) edcok eccok description l l error(s) present in current sector (1), (2) or (3) applies: lh (1) ecd overlooked (2) error corrected (3) error(s) present in header byte with form2 (1) edc overlooked, hlor (2) error(s) present in p parity byte h h no error(s) in current sector
?6 cxd1803aq/ar bit 1: cmode (correction mode) bit 0: cform (correction form) indicates the mode and form of the current sector whom the decoder has discriminated to correct errors when the decoder is operating in the real-time correction or repeat correction mode. 2.2.2. decsts (decoder status) register bit 1: shrtsct (short sector) indicates that the sync mark interval was less than 2351 bytes. this sector does not remain in the buffer memory. bit 0: nosync indicates that the sync mark was inserted because one was not detected in the prescribed position. 2.2.3. hdrflg (header flag) register indicates the error flags of the header and sub header register bytes. 2.2.4. hdr (header) register this is a 4-byte register which indicates the current sector header byte. by setting the address to 03 hex and reading out the data in sequence, the sub cpu can ascertain the values of the current sector header bytes from the minute byte. 2.2.5. shdr (sub header) register this is a 4-byte register which indicates the current sector sub header byte. by setting the address to 04 hex and reading out the data in sequence, the sub cpu can ascertain the values of the current sector sub header bytes from the file byte. the contents of the hdrflg, hdr and shdr registers indicate: (1) the corrected value in the real-time correction or repeat correction mode (2) value of the raw data from the drive in the monitor-only or write-only mode the cmome and cmode bits (bits 1, 0) of eccsts indicate the form and mode of the sector the decoder has discriminated by the raw data from the drive. due to erroneous corrections, the values of these bits may be at variance with those of the hdr register mode byte and shdr register submode byte bit 5. cform cmode 'x' 'l' mode1 'l' 'h' mode2, form1 'h' 'h' mode2, from2
?7 cxd1803aq/ar 2.2.6. cmadr-h (current minute address high) register indicates the upper 8 bits of the buffer memory in which the current sector (after completion of correction) minute byte is written. (the lower 10 bits are 00 hex .) 2.2.7. intsts (interrupt status) register the value of each bit in this register indicates that of the corresponding interrupt status. these bits are not affected by the values of the intmsk register bits. bit 7: drvovrn (drive overrun) bit 6: dectout (decoder time out) bit 4: rtadpend (real-time adpcm end) bit 3: hdmacmp (host dma complete) bit 2: decint (decoder interrupt) bit 1: bfwrdy (buffer write ready) bit 0: bfempt (buffer empty) 2.2.8. rddata (cpu buffer read data) the buffer data is read out from this register. 2.2.9. adpci (adpcm coding information) register bit 7: mute this is high when the da data is muted. bit 6: emphasis this is high when emphasis is applied to the adpcm data. bit 5: adpbusy this is high for adpcm decoding. bit 4: bitlngth (bit length) indicates the bit length of the coding information for adpcm playback. high: 8 bits low: 4 bits bit 3: smadpbsy (sound map adpcm busy) this is high during sound map adpcm playback. bit 2: fs (sampling frequency) indicates the sampling frequency of adpcm playback. high: 18.9 khz low: 37.8 khz bit 1: rtadpbsy (real-time adpcm busy) this is high during real-time adpcm playback. bit 0: s/m (stereo/monaural) indicates the coding information stereo or monaural for adpcm playback. high: stereo low: monaural 2.2.10. hxfrc-l (host transfer counter-low)
?8 cxd1803aq/ar 2.2.11. hxfrc-h (host transfer counter-high) the hxfrc counter indicates the number of remaining bytes in the data to be transferred between the scsi controller and the buffer memory. if sound map data is to be transferred before the data is transferred (immediately after the sub cpu has set the bfrd and bfwr bits (bits 7 and 6) of the dmactl register high), 2304 (900 hex ) is loaded into hxfrc. at any other time, the hxfr value is loaded. hxfrc is decremented when data is read from the buffer memory (bfrd is high) or when the ic accepts data from the scsi controller (bfwr is high). therefore, the sub cpu cannot read the hxfrc value during transfer of data between the scsi controller and the ic. the values of hxdrc and the write register hxfr are almost always different. 2.2.12. hadrc-l (host address counter-low) 2.2.13. hadrc-m (host address counter-middle) this counter keeps the addresses which write or read the data with the scsi controller into/from the buffer. if sound map data is to be transferred before the data is transferred, any of 600c hex , 6a0c hex or 740c hex (when connected to 32k-byte buffer memory) is loaded into hadrc. at any other time, the hadr (sub cpu register) value is loaded. when data from the scsi controller is written into the buffer or data to the scsi controller is read from the buffer, the hadrc value is output from ma0 to 16. hadrc is incremented each time one byte of data from the drive is read from the buffer (bfrd is high) or written into the buffer (bfwr is high). therefore, the sub cpu cannot read the hadrc value during transfer of data between the scsi controller and the ic. the values of hadrc and the write register hadr are almost always different. the upper two bits of hadrc are in hxfrc-h. 2.2.14. dadrc-l 2.2.15. dadrc-m the dadrc value is incremented before the data from the drive is written into buffer memory. therefore, the sub cpu can not read the dadrc value during decoder write-only or repeat correction modes. the upper two dadrc bits are in hxfrc-h. 2.2.16. cadrc-l 2.2.17. cadrc-m 2.2.18. cadrc-h bit 6: cbfrdrdy (sub cpu buffer read ready) the sub cpu can read the rddata register when this bit is high. bit 5: cbfwrrdy (sub cpu buffer write ready) the sub cpu can write in the wrdata register when this bit is high. bit 2: cadrc17 cadrc bit 17 (msb). bit 1: pdata (pointer data) the buffer memory pointer bit value can be read from this bit. bit 0: cadrc16 cadrc bit 16.
?9 cxd1803aq/ar reg adr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 drvif 00 c2po lch bck bck bck lsb 'l' 'l' l1st low red md1 md0 1st config 01 'l' xslow 'l' ram ram 9bit clk hclk 1 sz1 sz0 ram dis dis config 02 scyc scyc spe spmj sm damix dacout prty 2 1 0 ctl ctl bf2 dis en ctl decctl 03 en ecc mode from auto dec dec dec dladr str sel sel dist md2 md1 md0 dladr 04 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l dladr 05 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m dladr 06 'l' 'l' 'l' 'l' 'l' 'l' bit17 bit16 -h chpctl 07 sm rt cdda cd- sw rps dbl 'l' mute mute mute da open tart spd wrdata 08 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 intmsk 09 drv dec 'l' rtadp hdma dec bf bf ovrn tout end cmp int wrdy empt clrctl 0a chp 'l' 'l' rtadp smadp 'l' pre rst clr clr data sync clrint 0b drv dec 'l' rtadp hdma dec bf bf ovrn tout end cmp int wrdy empt hxfr 0c bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l hxfr 0d dis 'l' hadr hadr bit11 bit10 bit9 bit8 -h hxfrc bit17 bit16 hadr 0e bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l hadr 0f bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m dadrc 10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l dadrc 11 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m dadrc 12 'l' 'l' 'l' 'l' 'l' 'l' bit17 bit16 -h 13 | 'l' 'l' 'l' 'l' 'l' 'l' 'l' 'l' 14 sub cpu write registers (1)
?0 cxd1803aq/ar reg adr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cadrc 15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l cadrc 16 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m cadrc 17 'l' cpu cdma 'l' 'l' 'l' bir17 bit16 -h src en dmactl 18 bfrd bfwr smen 'l' 'l' 'l' 'l' 'l' adpmnt 19 rtadp bit16 bit15 bit14 bit13 bit12 bit11 bit10 en smci 1a 'l' emph 'l' bit 'l' fs 'l' s/m asis lngth rtci 1b 'l' emph 'l' bit 'l' fs adpmnt s/m asis lngth bit17 atv0 1c bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 atv1 1d bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 atv2 1e bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 atv3 1f bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sub cpu write registers (2)
?1 cxd1803aq/ar reg adr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 eccsts 00 edc erin cor cor edc ecc c c all0 blk inh done ok ok mode form decsts 01 shrt no sct sync hdrflg 02 min sec blo mode file chan sub ci ck nel mode hdr 03 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 shdr 04 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cmadr 05 bit17 bit16 bit15 bit14 bit13 bit12 bit11 bit10 -h intsts 07 drv dec rtadp hdma dec bf bf ovrn tout end cmp int wrdy empt rddata 08 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adpci 09 mute emph adp bit smadp fs rtadp s/m asis bsy lngth bsy bsy hxfrc 0a bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l hxfrc 0b dc hc dc hc bit11 bit10 bit9 bit8 -h bit17 bit17 bit16 bit16 hadrc 0c bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l hadrc 0d bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m dadrc 0e bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l dadrc 0f bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m 10 | 1c cadrc 1d bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 -l cadrc 1e bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 -m cadrc 1f cbf cbf bit17 p bit16 -h rdrdy wrdry data sub cpu read registers for hxfrc-h, dc and hc represent dadrc and hasrc respectively.
?2 cxd1803aq/ar 3. connection with buffer memory 3.1.memory types the dram pin input, cnfig1 register ramsz1, ramsz0 and 9bitram bits (bits 4 to 2) are set depending on the buffer memory connected to the ic. figs. 3-1 to 3.5 show examples of connection. 3.2.access time the relationship between the decoder clock frequency (mhz) and minimum access time required by the memory (preliminary value, ns) when the config1 register xslow is high is shown below. when xslow is low and clock frequency is 16.9344 mhz, sram access time is 500 ns and dram access time is 300 ns. dram ramsz1 ramsz0 9bitram memory size 'l' 'l' 'l' 'l' 32k w 8 b sram 'l' 'l' 'l' 'h' 32k w 9 b sram 'l' 'l' 'h' 'l' 32k w 8 b sram 2 'l' 'l' 'h' 'h' 32k w 9 b sram 2 'l' 'h' 'l' 'l' 128k w 8 b sram 'l' 'h' 'l' 'h' 128k w 9 b sram 'l' 'h' 'h' 'l' 128k w 8 b sram 2 'l' 'h' 'h' 'h' 128k w 9 b sram 2 'h' 'h' 'h' 'l' 256k w 4 b dram 2 clock frequency access time sram dram 16.9344 120 110 20.0000 100 90 24.0000 70 80 32.0000 50 50 33.8688 45 50
?3 cxd1803aq/ar cxd1803aq/ar 32kb sram ma14 to 0 mdb7 to 0 mdbp xmoe xmwr xme0 a14 to 0 i/o8 to 1 i/o9 /oe /wr /ce * 1 * 2 * 1 cxd1803aq/ar 32kb sram ma14 to 0 mdb7 to 0 mdbp xmoe xmwr ma15 a14 to 0 i/o8 to 1 i/o9 /oe /wr /ce 32kb sram a14 to 0 i/o8 to 1 i/o9 /oe /wr /ce fig. 3-2 connection to 64k-byte sram fig. 3-1 connection to 32k-byte sram * 1 connect to 9 bits / word sram when performing erasure correction. * 2 connect /ce to xme0 or ground.
?4 cxd1803aq/ar cxd1803aq/ar 128kb sram ma16 to 0 mdb7 to 0 mdbp xmoe xmwr xme0 a16 to 0 i/o8 to 1 i/o9 /oe /wr /ce1 * 1 * 2 cxd1803aq/ar 128kb sram a14 to 0 i/o8 to 1 i/o9 /oe /wr /ce1 * 1 128kb sram a14 to 0 i/o8 to 1 i/o9 /oe /wr /ce1 ma14 to 0 mdb7 to 0 mdbp xmoe xmwr xme0 xme1 fig. 3-3 connection to 128k-byte sram * 1 connect to x9 sram when performing erasure correction. * 2 connect /ce1 to xme0 or ground. * 3 connect ce2 to vdd. fig. 3-4 connection to 256k-byte sram
?5 cxd1803aq/ar cxd1803aq/ar ma8 to 0 mdb7 to 4 mdb3 to 0 xras xcas xmwr a8 to 0 i/o4 to 1 /ras /cas /we 128kb dram a8 to 0 i/o4 to 1 /ras /cas /we 128kb dram fig. 3-5 connection to 256k-byte dram * 4 connect dram /oe pin to ground.
sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion. package outline unit : mm cxd1803aq cxd1803ar cxd1803aq/ar ?6

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